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HD74HC292/HD74HC294
Programmable Frequency Divider/Digital Timer
REJ03D0608-0200 (Previous ADE-205-486) Rev.2.00 Jan 31, 2006
Description
This device divides the incoming clock frequency by a number (a power of 2) that is preset by the Programming inputs. It has two Clock inputs, either of which may be used as a clock inhibit. The device also has an active-low Reset, which initializes the internal flip-flop states. Test Point outputs (TP1, TP2, TP3) are provided with HD74HC292 to facilitate incoming inspections. Test Point output is provided with HD74HC294 to facilitate incoming inspections.
Features
* * * * * * High Speed Operation: tpd (Clock to Q) = 16 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 A max Low Quiescent Supply Current: ICC (static) = 4 A max (Ta = 25C) Ordering Information
Part Name HD74HC292P HD74HC294FPEL Package Type DILP-16 pin SOP-16 pin (JEITA) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) Package Abbreviation P -- EL (2,000 pcs/reel) Taping Abbreviation (Quantity)
PRSP0016DH-B FP (FP-16DAV) Note: Please consult the sales office for the above package availability.
Function Table
CLR L H H H H high level low level CLK1 X L H X CLK2 X L X H Q Output Mode Cleared to L Count Count Inhibit Inhibit
H: L:
Rev.2.00 Jan 31, 2006 page 1 of 9
HD74HC292 / HD74HC294 HD74HC292
Programming Inputs E L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H D L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H C L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H B L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H A L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H Binary Inhibit Inhibit 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 3 4 5 6 7 8 9
Frequency Division Q Out Decimal Inhibit Inhibit 4 8 16 32 64 128 256 512 1,024 2,048 4,096 8,192 16,384 32,768 65,536 131,072 262,144 524,288 1,048,576 2,097,152 4,194,304 8,388,608 16,777,216 33,554,432 67,108,864 134,217,728 268,435,456 536,870,912 1,073,741,824 2,147,483,648 Binary Inhibit Inhibit 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9
TP1 Decimal Inhibit Inhibit 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 Binary Inhibit Inhibit 2 2 2 2 2 2 2 2 2 2 2 2
17 17 17 17 17 17 17 17 17 17 17 17
TP2 Decimal Inhibit Inhibit 131,072 131,072 131,072 131,072 131,072 131,072 131,072 131,072 131,072 131,072 131,072 131,072 Binary Inhibit Inhibit 2 2 2 2 2 2
24 24 24 24 24 24 2 2 4 4 6 6 8 8
TP3 Decimal Inhibit Inhibit 16,777,216 16,777,216 16,777,216 16,777,216 16,777,216 16,777,216 4 4 16 16 64 64 256 256 1,024 1,024 4,096 4,096 16,384 16,384 65,536 65,536 262,144 262,144 1,048,576 1,048,576 4,194,304 4,194,304 16,777,216 16,777,216
2 2 2 2 2 2 2 2
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Disabled LOW Disabled LOW 2 2 2 2 2 2
3 3 5 5 7 7 9 9
8 8 32 32 128 128 512 512 2,048 2,048 8,192 8,192 32,768 32,768 131,072 131,072
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10 10 12 12 14 14 16 16 18 18 20 20 22 22 24 24
Disabled LOW Disabled LOW 2 2 2 2 2 2 2 2
3 3 5 5 7 7 9 9
2 2 8 8 32 32 128 128 512 512 2 2 2 2 2 2 2 2
11 11 13 13 15 15 17 17
Rev.2.00 Jan 31, 2006 page 2 of 9
HD74HC292 / HD74HC294 HD74HC294
Programming Inputs D L L L L L L L L H H H H H H H H C L L L L H H H H L L L L H H H H B L L H H L L H H L L H H L L H H A L H L H L H L H L H L H L H L H Frequency Division Q Output TP Output Binary Decimal Binary Decimal Inhibit Inhibit Inhibit Inhibit Inhibit Inhibit Inhibit Inhibit 2 9 2 4 2 512 23 8 29 512 4 9 2 16 2 512 25 32 29 512 26 64 29 512 7 2 128 Disabled LOW 28 256 22 4 29 512 23 8 10 4 2 1,024 2 16 211 2,048 25 32 12 6 2 4,096 2 64 213 8,192 27 128 214 16,384 28 256 15 9 2 32,768 2 512
Pin Arrangement
* HD74HC292
B E TP1 CLK1 CLK2 TP2 Q GND 1 2 3 4 5 6 7 8 (Top view) 16 15 14 13 12 11 10 9 VCC C D TP3 NC CLR A NC
Rev.2.00 Jan 31, 2006 page 3 of 9
HD74HC292 / HD74HC294 * HD74HC294
B A TP CLK1 CLK2 NC Q GND 1 2 3 4 5 6 7 8 (Top view) 16 15 14 13 12 11 10 9 VCC C D NC NC CLR NC NC
Logic Diagram
* HD74HC292
CLR CLK1
R R CK
CLK2
R R MC CK
R
R
TP1
0 1 14 13
D
D
D
R R MC CK
R
R
TP2
D
D
D
D
A B C D E
2 4 8 6
12 11 10 9
R R MC CK
R
R
TP3
D
D
D
8 7 6 5
R R MC CK
R
R
Q
D
D
D
4 3 2
Rev.2.00 Jan 31, 2006 page 4 of 9
HD74HC292 / HD74HC294 * HD74HC294
CLR CLK1 CLK2
0 1
14 13 12 11 10 9
TP
A B C D
1 2 4 8
8
7 6 5 4 3 2
Q
Absolute Maximum Ratings
Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC VIN, VOUT IIK, IOK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to VCC +0.5 20 25 50 500 -65 to +150 Unit V V mA mA mA mW C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Symbol VCC VIN, VOUT Ta tr, tf Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500 0 to 400 Unit V V C ns Conditions
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics.
Rev.2.00 Jan 31, 2006 page 5 of 9
HD74HC292 / HD74HC294
Electrical Characteristics
Item Input voltage Symbol VCC (V) VIH VIL 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- Ta = 25C Typ Max -- -- -- -- -- -- -- 0.5 -- 1.35 -- 1.8 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 4.0 Ta = -40 to+85C Unit Min Max 1.5 -- V 3.15 -- 4.2 -- V -- 0.5 -- 1.35 -- 1.8 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 40 V Test Conditions
Output voltage
VOH
Vin = VIH or VIL IOH = -20 A
VOL
V
Vin = VIH or VIL
IOH = -4 mA IOH = -5.2 mA IOL = 20 A
Input current Quiescent supply current
Iin ICC
IOL = 4 mA IOL = 5.2 mA A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A
Switching Characteristics
(CL = 50 pF, Input tr = tf = 6 ns)
Item Maximum clock frequency Propagation delay time Removal time Symbol VCC (V) fmax 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- Min -- -- -- -- -- -- 100 20 17 80 16 14 -- -- -- -- Ta = 25C Typ Max -- -- -- -- 16 -- -- -4 -- -- 14 - -- 5 -- 5 5 27 31 600 120 100 -- -- -- -- -- -- 75 15 13 10 Ta = -40 to +85C Unit Min Max -- -- -- -- -- -- 125 25 21 100 20 17 -- -- -- -- 4 21 24 750 150 125 -- -- -- -- -- -- 95 19 16 10 MHz Test Conditions
tPLH
ns
Clock to output
trem
ns
Pulse width
tw
ns
Output rise/fall time Input capacitance
tTLH tTHL Cin
ns
pF
Rev.2.00 Jan 31, 2006 page 6 of 9
HD74HC292 / HD74HC294
Test Circuit
* HD74HC292
VCC VCC Output Input A
See Function Table
B C D E CK1 CK2 CLR
TP1 Output TP3 Output Q CL = 50 pF CL = 50 pF CL = 50 pF
Pulse Generator Zout = 50 Input Pulse Generator Zout = 50
Note : 1. CL includes probe and jig capacitance.
* HD74HC294
VCC VCC Output TP CL = 50 pF Output CK1 CK2 CLR Q CL = 50 pF
Input
A
See Function Table
B C D
Pulse Generator Zout = 50 Input Pulse Generator Zout = 50
Note : 1. CL includes probe and jig capacitance.
Rev.2.00 Jan 31, 2006 page 7 of 9
HD74HC292 / HD74HC294
Waveforms
6ns 6ns VCC
90% CLR 10% trem 6ns 6ns 6ns 50%
90% 50% 10%
GND
90% CLK 50% 50% 10%
90% 50% 10%
90% 50% 10%
VCC
GND tPHL 90% VOH 50% 10% VOL
tPLH 90% Q or TP 50% 10% tTLH 90%
tPHL
tPLH
50% 10% tTHL
50% 10%
tTLH
tTHL
Note : 1. Input pulse : PRR1MHz, duty cycle 50%, tr 6ns, tf 6ns
Rev.2.00 Jan 31, 2006 page 8 of 9
HD74HC292 / HD74HC294
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
L
1
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c
0.00
0.10
0.20 2.20
0.34
0.40
0.46
0.15
1
0.20
0.25
A
c
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.2.00 Jan 31, 2006 page 9 of 9
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